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FPGA-based High Power Pulsed Current Source Controller
Today, new technologies such as power electronic switches or circuit breakers for DC grids are requested with ever increasing capabilities, but suitable test devices to support their development do not exist. In the last years, ETH Zurich undertook the development of a flexible pulsed current source to supply arbitrarily shaped high-current pulses with system voltage of 10kV and nominal currents up to 24 kA nominal. It is achieved by a parallel arrangement of eight individually controlled buck converters (IGBT) and switchable energy-absorbing devices (MOV). This source can ramp up to the nominal current and down to zero within less than half a millisecond while maintaining an output current over several tens of milliseconds. The control of this source is very demanding and the topic of the present thesis project.
Keywords: HDL, hardware-software co-design, control engineering, high voltage/high power
The control system consists of mainly two parts: one central controller and a satellite controller for each of the eight buck converters. In order to fulfill the stringent requirements, the system is heavily based on field programmable gate arrays (FPGAs). Your main task would be to advance the development of the central controller based on an Intel Cyclone V SoC (System on Chip) with the goal of a fully working 8-channel prototype towards the end of your thesis. This will include hardware/software co-design, i.e. designing the programmable logic as well as the corresponding software on the SoC, developing testbenches for reliable testing of your code/firmware and proper operation with the satellite boards.
**Prerequisites**
- HDL (VHDL/Verilog) and circuit design
- C programming in an SoC environment
- Interest power electronic applications and high-speed control
- MATLAB or Python for evaluation is beneficial
**Character**
- 20% Literature study
- 50% HDL satellite firmware design and C-programming
- 30% Measurements, documentation and validation
The control system consists of mainly two parts: one central controller and a satellite controller for each of the eight buck converters. In order to fulfill the stringent requirements, the system is heavily based on field programmable gate arrays (FPGAs). Your main task would be to advance the development of the central controller based on an Intel Cyclone V SoC (System on Chip) with the goal of a fully working 8-channel prototype towards the end of your thesis. This will include hardware/software co-design, i.e. designing the programmable logic as well as the corresponding software on the SoC, developing testbenches for reliable testing of your code/firmware and proper operation with the satellite boards.
**Prerequisites**
- HDL (VHDL/Verilog) and circuit design - C programming in an SoC environment - Interest power electronic applications and high-speed control - MATLAB or Python for evaluation is beneficial
**Character**
- 20% Literature study - 50% HDL satellite firmware design and C-programming - 30% Measurements, documentation and validation
- design and implement a controller for up to 8 high power channels
- test, document and validate your design
- design and implement a controller for up to 8 high power channels - test, document and validate your design
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch),
Prof. Dr. Christian Franck (franck@eeh.ee.ethz.ch)
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch), Prof. Dr. Christian Franck (franck@eeh.ee.ethz.ch)