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Low Power FPGA as Machine Learning Accelerator
Implement and evaluate a given image detection algorithm on a low power FPGA plattform
Keywords: Digital design (HDL), Low Power Electronics, Machine Learning
With more complex machine learning (ML) algorithms being utilized in devices for the internet of things (IoT), an evaluation and comparison of current state of the art implementations for ML on low power FPGAs is desirable. Such FPGAs could then be used as computing accelerators in conjunction with a microcontroller, especially in power constrained environments on IoT nodes or edge devices. This could enable either more powerful ML algorithms on the IoT nodes, or reduce energy consumption and thus increase battery life of them. One example of such an application would be image detection on a data stream generated by a camera.
**Prerequisites**
- Machine learning (especially image recognition)
- Digital hardware design (HDL)
- Machine learning on microcontrollers (Firmware)
- MATLAB or Python for evaluation of results
**Character**
- 10% Literature study
- 40% HDL Design and Optimization
- 30% Microcontroller Firmware
- 20% Measurements and validation
With more complex machine learning (ML) algorithms being utilized in devices for the internet of things (IoT), an evaluation and comparison of current state of the art implementations for ML on low power FPGAs is desirable. Such FPGAs could then be used as computing accelerators in conjunction with a microcontroller, especially in power constrained environments on IoT nodes or edge devices. This could enable either more powerful ML algorithms on the IoT nodes, or reduce energy consumption and thus increase battery life of them. One example of such an application would be image detection on a data stream generated by a camera.
**Prerequisites**
- Machine learning (especially image recognition) - Digital hardware design (HDL) - Machine learning on microcontrollers (Firmware) - MATLAB or Python for evaluation of results
**Character**
- 10% Literature study - 40% HDL Design and Optimization - 30% Microcontroller Firmware - 20% Measurements and validation
- implementation of a given image detection ML algorithm on a low power FPGA platform
- implementation of the same algorithm on a Cortex M0 or M4 microcontroller
- evaluation in terms of comparing the energy consumption, computation speed and parallelization of the FPGA with a low power microcontroller
- implementation of a given image detection ML algorithm on a low power FPGA platform - implementation of the same algorithm on a Cortex M0 or M4 microcontroller - evaluation in terms of comparing the energy consumption, computation speed and parallelization of the FPGA with a low power microcontroller
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch), Dr. Michele Magno (michele.magno@pbl.ee.ethz.ch)
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch), Dr. Michele Magno (michele.magno@pbl.ee.ethz.ch)