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Neuromorphic HW Accelerator for FPGA-based Drones
To enable new applications on drone platforms, novel sensors coupled with with machine learning algorithms are essential. Such sensors are, for example, event-based cameras. They are fast (~kHz speed) and resilient to the environment (e.g. poor lighting conditions). To utilize the full potential of these cameras, neuromorphic computing is needed to process their output. Our FPGA-based drone platform is capable of operating such an event-based camera, and allows for efficient hardware acceleration of the computationally expensive neuromorphic algorithms.
Keywords: Digital design (HDL), Robotics, machine learning
Your task will be the evaluation on how a neuromorphic hardware accelerator can be implemented on our FPGA drone platform, as well as implementing it to be used with data from an event-based camera. Next to logic design, this thesis will also include writing a suitable tool chain to port given spiking neural networks onto your custom hardware accelerator. Finally, you will compare your implementation with the state of the art in terms of possible network size, latency, power consumption and maximum speed on different datasets.
**Prerequisites**
- Solid understanding of neuromorphic computing
- Solid HDL knowledge
- MATLAB or Python or C++ for pre-processing toolchain
**Character**
- 20% Literature study
- 50% Algorithm design, implementation and evaluation
- 20% Measurements and validation
- 10% Documentation
Your task will be the evaluation on how a neuromorphic hardware accelerator can be implemented on our FPGA drone platform, as well as implementing it to be used with data from an event-based camera. Next to logic design, this thesis will also include writing a suitable tool chain to port given spiking neural networks onto your custom hardware accelerator. Finally, you will compare your implementation with the state of the art in terms of possible network size, latency, power consumption and maximum speed on different datasets.
**Prerequisites**
- Solid understanding of neuromorphic computing - Solid HDL knowledge - MATLAB or Python or C++ for pre-processing toolchain
**Character**
- 20% Literature study - 50% Algorithm design, implementation and evaluation - 20% Measurements and validation - 10% Documentation
- design a neuromorphic accelerator (hw/sw co-design) for a state of the art FPGA platform
- build a toolchain to process NN-models for your accelerator
- design a neuromorphic accelerator (hw/sw co-design) for a state of the art FPGA platform - build a toolchain to process NN-models for your accelerator
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch), Dr. Michele Magno (michele.magno@pbl.ee.ethz.ch)
Dr. Christian Vogt (christian.vogt@pbl.ee.ethz.ch), Dr. Michele Magno (michele.magno@pbl.ee.ethz.ch)